This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-129661, filed Apr. 28, 2000; and No. 2000-165516, filed Jun. 2, 2000, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method of manufacturing a thin film transistor panel used in, for example, an active matrix type liquid crystal display device, particularly, to a method of manufacturing a thin film transistor panel, which permits lowering the manufacturing cost of a thin film transistor having a protective film of the channel region.
2. Description of the Related Art
In manufacturing a thin film transistor panel applied to an active matrix type liquid crystal display device, a transparent substrate is prepared consisting of, for example, glass and providing the base of the thin film transistor panel. In order to improve productivity, a large transparent substrate having a size corresponding to a plurality of thin film transistor panels is prepared, and the portions corresponding to a plurality of panels are collectively prepared up to a predetermined manufacturing step, followed by dividing the large transparent substrate into individual panels for application of the subsequent manufacturing steps. Also, in the case of manufacturing a thin film transistor panel equipped with a thin film transistor acting as a switching element, an anodic oxide film is formed on the surface of, for example, a gate line (scanning signal line) including the gate electrode of the thin film transistor so as to improve the breakdown voltage. Further, insulation breakdown takes place in the thin film transistor or the voltage-current characteristics of the thin film transistor are changed by static electricity generated when, for example, the oriented film is subjected to a rubbing treatment before the large transparent substrate is divided into the individual panels, or by the divided individual panels contacting another substance charged with a high voltage of, for example, static electricity. Under the circumstances, measures against static electricity are taken.
FIG. 20, which illustrates the prior art, is a plan view showing the equivalent circuit of a thin film transistor panel under the state that pixel electrodes, etc. are formed on a glass substrate having a size corresponding to a plurality of thin film transistor panels. A glass substrate 1 having a size corresponding to a plurality of thin film transistor panels is finally cut along a cut line 2 denoted by a dot-and-dash line so as to be divided into individual panels. In this case, the region surrounded by the cut line 2 forms a panel forming region 3 and the region surrounding the panel forming region 3 forms a panel non-forming region 4. Also, that region of the panel forming region 3 which is surrounded by a two dots-and-dash line forms a display region 5, and the region surrounding the display region 5 forms a non-display region 6.
Arranged within the display region 5 are a plurality of pixel electrodes 7 arranged to form a matrix, a plurality of thin film transistors 8 connected to these pixel electrodes 7, a plurality of scanning signal lines 9 arranged in the row direction for supplying a scanning signal to the thin film transistors 8, a plurality of data signal lines 10 arranged in the column direction for supplying a data signal to the thin film transistors 8, a plurality of auxiliary capacitance lines 11 arranged in the row direction and forming an auxiliary capacitance section Cs between the pixel electrode 7 and the auxiliary capacitance line 11, a protective ring 13 including a jumper line 12 arranged to surround a plurality of the pixel electrodes 7, a plurality of protective elements 14 arranged on the outside of the protective ring 13 and each consisting of two protective thin film transistors arranged to face each other with the scanning signal line 9 interposed therebetween, and a plurality of protective elements 15 arranged on the outside of the protective ring 13 and each consisting of two protective thin film transistors arranged to face each other with the data signal line 10 interposed therebetween. Further, power supply lines 16 are arranged to form a lattice within the panel non-forming region 4.
The left edge portion of each of the scanning signal lines is connected to the power supply line 16 via a connection pad (scanning electrode terminal) 18 on the output side arranged within a semiconductor chip mounting region 17 denoted by a dotted line within the non-display region 6. The upper edge portion of each of the data signal lines 10 is connected to the power supply line 16 via a connection pad (data electrode terminal) 20 on the output side arranged within a semiconductor chip mounting region 19 denoted by a dotted line within the non-display region 6. Connection pads 21, 22 on the input side, which are arranged within the semiconductor chip mounting regions 17, 19, respectively, are connected to external connection terminals 23 formed at predetermined positions within the non-display region 6 via wirings 24. These external connection terminals 23 are connected to the power supply line 16. The left edge portion of each of the auxiliary capacitance lines 11 is connected to the power supply line 16 via a common line 25 and a connection pad 26, which are arranged on the outside of the right side portion of the protective ring 13. Incidentally, the common line 25 is connected to the protective ring 13 in some cases.
The gate electrode G and the source electrode S of the protective thin film transistor on the upper side, which is included in the protective element 14 arranged on the side of the scanning signal line, are connected to the scanning signal line 9, and the drain electrode of the particular protective thin film transistor is connected to the protective line 13. On the other hand, the gate electrode G and the source electrode S of the lower protective thin film transistor, which is included in the protective element 14 on the side of the scanning signal line, are connected to the protective ring 13, and the drain electrode D of the particular thin film transistor is connected to the scanning signal line 9. Further, the gate electrode G and the source electrode S of the protective thin film transistor on the left side, which is included in the protective circuit 15 on the side of the data signal line, are connected to the protective ring 13, and the drain electrode D of the particular thin film transistor is connected to the data signal line 10. Still further, the gate electrode G and the source electrode S of the protective thin film transistor on the right side, which is included in the protective element 15 arranged on the side of the data signal line, are connected to the data signal line 10, and the drain electrode D of the particular thin film transistor is connected to the protective ring 13.
The method of manufacture of a thin film transistor panel of the construction described above will now be described with reference to FIG. 21. In the first layer forming step S1 shown in FIG. 21, an Al-based metal film (not shown) such as an Al film or an Al alloy film is formed on the upper surface of a glass substrate. Then, in the first photoresist forming step S2 shown in FIG. 21, a first photoresist film is formed on the upper surface of the Al-based metal film. Further, in the scanning signal line forming step S3 shown in FIG. 21, the Al-based metal film is etched with the first photoresist film used as a mask, followed by peeling off the first resist film.
As a result, formed on the upper surface of the glass substrate 1 are the gate electrode G of the thin film transistor, the scanning signal line 9, the auxiliary capacitance line 11, a lower protective ring 13a, and a lower layer connection pad 18, each consisting of the Al-based metal film, as shown in FIG. 22. Incidentally, the xe2x80x9clower protective ring 13axe2x80x9d noted above represents the upper side portion, the lower side portion and the right side portion of the protective ring 13 shown in FIG. 20. Also formed are the power supply line 16, the connection pads 21, 22, the external connection terminal 23, the wiring 24, the common line 25, the connection pad 26, etc. Incidentally, the protective thin film transistors included in each of the protective elements 14 and 15 are formed in substantially the same manner as in the formation of the thin film transistor 8 and, thus, the description is omitted in respect of the formation of the protective thin film transistors noted above.
Then, in the second photoresist forming step S4 shown in FIG. 21, a second photoresist film 29a is formed on the lower layer connection pad 18a, and a second photoresist film 29b is formed on the connecting portion of the lower protective ring 13a at which the lower protective portion 13a is connected to the jumper line 12 shown in FIG. 20, as shown in FIG. 22. Further, in the anodic oxidation step S5 shown in FIG. 21, one electrode of the power supply line 16 shown in FIG. 20 is subjected to an anodic oxidation so as to form an anodic oxide film 30 on the surfaces of the gate electrode G of the thin film transistor 8, the scanning signal line 9, the auxiliary capacitance line 11, etc. as shown in FIG. 23. In this case, an anodic oxide film is not formed on the surfaces of the lower layer connection pad 18a and the connecting portion of the lower portion protective ring 13a, which are covered with the second photoresist films 29a, 29b, respectively. Then, the second photoresist films 29a, 29b are peeled off.
Then, in the three layers forming step S6 shown in FIG. 21, a gate insulating film 31 consisting of silicon nitride, a semiconductor film 32 consisting of an intrinsic amorphous silicon, and a protective film-forming film 33 consisting of silicon nitride are successively formed as shown in FIG. 24. Further, in the third photoresist forming step S7 shown in FIG. 21, the upper surface of the protective film-forming film 33 is coated with a third photoresist film, followed by applying a light exposure from the back surface with the gate electrode G, etc. used as a mask. At the same time, a light exposure is also applied from the front surface by using a photomask (not shown). Then, a developing treatment is applied. As a result, a third photoresist film 34a is formed on the upper surface of the protective film-forming film 33 on the gate electrode G of the thin film transistor 8, as shown in FIG. 24. Also, a photoresist film 34b is formed on the upper surface of the protective film-forming film 33 in the crossing region of the lines 9 and 10.
Then, in the protective film forming step S8 shown in FIG. 21, the protective film-forming film 33 is subjected to a wet etching with the third photoresist films 34a, 34b used as a mask. As a result, protective films 33a, 33b are formed below the third photoresist films 34a, 34b, respectively, as shown in FIG. 25. Then, the third photoresist films 34a, 34b are peeled off. In this case, the protective film 33b serves to improve the breakdown voltage in the crossing region of the lines 9 and 10. Also, the protective film 33a serves to protect the channel region of the semiconductor film 32. The protective film 33a will be described in detail herein later in conjunction with the manufacturing process of the thin film transistor.
Where semiconductor film 32 has defects such as pin holes when the protective film-forming film 33 is subjected to a wet etching, the etchant permeates into the semiconductor film 32 so as to arrive at the gate insulating film 31, with the result that pin holes are formed in the gate insulating film 31, or the semiconductor film 32 is damaged. However, since the anodic oxide film 30 is formed on the surface of the scanning signal line 9, etc. including the gate electrode G, a short circuit between the gate electrode 30 and the source electrode S or between the gate electrode 30 and the drain electrode D is prevented. It is also possible to prevent the breakdown voltage of the gate insulating film 31 from being substantially lowered.
Then, in the n-type amorphous silicon film forming step S9 shown in FIG. 21, an n-type amorphous silicon film 35 is formed as shown in FIG. 26. Further, in the three conductive layers forming step S10 shown in FIG. 21, a Cr film 36, an Al-based metal film 37, and a Cr film 38 are successively formed as shown in FIG. 26.
In the subsequent step of the fourth photoresist forming step S11 shown in FIG. 21, fourth photoresist films 39a to 39d are formed in predetermined positions on the upper surface of the upper Cr film 38, as shown in FIG. 26. In this case, the fourth photoresist films 39a and 39b are for forming the drain electrode D and the source electrode S, respectively, of the thin film transistor 8. The third photoresist film 39c is for forming the data signal line 10 and the lower layer connection pad. Further, the fourth photoresist film 39d is for forming the remaining portion of the protective ring 13, i.e., for forming the left side portion of the protective ring 13 shown in FIG. 20.
Then, in step S12 for forming the data signal line, etc. shown in FIG. 21, the Cr film 38, the Al-based metal film 37 and the Cr film 36 are etched with the fourth photoresist films 39a to 39d used as a mask. Further, in the device area forming step S13 shown in FIG. 21, the n-type amorphous silicon film 35 and the semiconductor film 32 are etched with the fourth photoresist films 39a to 39d used as a mask.
As a result, the data signal line 10 and the lower layer connection pad 20a are formed as shown in FIG. 27. In this case, each of the data signal line 10 and the lower layer connection pad 20 is of a laminate structure consisting of the semiconductor film 32, the n-type amorphous silicon film 35, the Cr film 36, the Al-based metal film 37 and the Cr film 38, which are laminated in the order mentioned as viewed from below.
Also, in the region of forming the thin film transistor 8, etc., a semiconductor film 32a is formed in a predetermined position on the upper surface of the gate insulating film 31. Also, the drain electrode D and the source electrode S are formed on both sides above the upper surface of the protective film 33a and on both sides above the semiconductor film 32a. In this case, each of the drain electrode D and the source electrode S is of a laminate structure consisting of the n-type amorphous silicon film 35, the Cr film 36, the Al-based metal film 37 and the Cr film 38, which are laminated in the order mentioned as viewed from below. It should be noted that the protective film 33a serves to prevent the semiconductor film 32a, made of amorphous silicon, from being etched in the step of etching the n-type amorphous silicon film 35 on the channel region of the thin film transistor 8. As a result, the characteristics of the thin film transistor are prevented from being deteriorated.
Further, a remaining portion 13b of the protective ring 13, i.e., the left side portion of the protective ring 13 shown in FIG. 20, is formed. In this case, the remaining portion 13b of the protective ring 13, which is herein after referred to as the xe2x80x9cupper portion protective ring 13xe2x80x9d, is of a laminate structure consisting of the semiconductor film 32, the n-type amorphous silicon film 35, the Cr film 36, the Al-based metal film 37 and the Cr film 38, which are laminated in the order mentioned as viewed from below. Then, the fourth photoresist films 39a to 39d are peeled off.
Then, in the overcoat film forming step S14 shown in FIG. 21, an overcoat film 41 (see FIG. 28) consisting of silicon nitride is formed. Further, in the fifth photoresist forming step S15 shown in FIG. 21, a fifth photoresist film (not shown) is formed on the upper surface of an overcoat film (upper insulating film) 41. Still further, in the contact hole forming step S16 shown in FIG. 21, contact holes are made in predetermined positions of the overcoat film 41 and the gate insulating film 31 with the fifth photoresist film used as a mask, followed by peeling off the fifth photoresist film.
As a result, in the region for forming the thin film transistor 8, etc., a contact hole 42 is formed in that region of the overcoat film 41 which corresponds to the source electrode S, as shown in FIG. 28. On the other hand, in the region for forming the jumper line 12 of the protective ring 13, a contact hole 43 is formed in those portions of the overcoat film 41 and the gate insulating film 31 which correspond to the connecting portion of the lower portion protective ring 13a. Also, a contact hole 44 is formed in that portion of the overcoat film 41 which corresponds to the connecting portion of the upper portion protective ring 13b. Further, in the region for forming the connection pad 20, a contact hole 45 is formed in that portion of the overcoat film 41 which corresponds to the lower layer connection pad 20a. Still further, in the region for forming the connection pad 18, a contact hole 46 is formed in those portions of the overcoat film 41 and the gate insulating film 31 which correspond to the lower layer connection pad 18a. 
Then, in the ITO (Indium Tin Oxide) film forming step S17 shown in FIG. 21, an ITO film 47 is formed as shown in FIG. 29. Further, in the sixth photoresist forming step S18 shown in FIG. 21, sixth photoresist films 48a to 48d are formed in predetermined positions on the upper surface of the ITO film 47, as shown in FIG. 29. In this case, the sixth photoresist film 48a is for forming the pixel electrode 7. The sixth photoresist film 48b is for forming the jumper line 12 of the protective ring 13. Further, the sixth photoresist films 48c and 48d are for forming the upper layer connection pad.
Then, in step S19 for forming the pixel electrode, etc. shown in FIG. 21, the ITO film 47 is etched with the sixth photoresist films 48a to 48d used as a mask, followed by peeling off the sixth photoresist films 48a to 48d. As a result, in the region for forming the thin film transistor 8, etc., the pixel electrode 7 consisting of the ITO film is formed in a predetermined position on the upper surface of the overcoat film 41 in a manner to be connected to the source electrode S via the contact hole 42, as shown in FIG. 30. Also, in the region for forming the jumper line 12 of the protective ring 13, a jumper line 12 consisting of the ITO film is formed in a predetermined position on the upper surface of the overcoat film 41. In this case, one end portion of the jumper line 12 is connected to the lower portion protective ring 13a via the contact hole 43, and the other end portion of the jumper line 12 is connected to the upper portion protective ring 13b via the contact hole 44.
Also, in the region for forming the connection pad 20, the upper layer connection pad 20b consisting of the ITO film is formed in a predetermined position on the upper surface of the overcoat film 41 in a manner to be connected to the lower layer connection pad 20a via the contact hole 45. Further, in the region for forming the connection pad 18, the upper layer connection pad 18b consisting of the ITO film is formed in a predetermined position on the upper surface of the overcoat film 41 in a manner to be connected to the lower layer connection pad 18a via the contact hole 46. In this case, if the connection pad 18 is formed of only the lower layer connection pad 18a consisting of the Al-based metal layer, the surface of the connection pad 18 is exposed to the outside in the contact hole 46 so as to be oxidized. In the present invention, however, such a problem is not generated because the upper layer connection pad 18b consisting of the ITO film is formed on the surface of the lower layer connection pad 18a. The thin film transistor panel as shown in FIG. 20 is obtained by the steps described above. In the thin film transistor panel thus obtained, the ITO film constituting the pixel electrode 7 is positioned on the top side of the thin film transistor 8 and, thus, is called a TOP-ITO structure in some cases.
It should be noted that, in manufacturing the thin film transistor panel, static electricity is generated when, for example, the oriented film is subjected to a rubbing treatment before the panel is cut along the cut line 2. However, since all the wirings within the panel forming region 3 are connected to the power supply line 16 within the panel non-forming region 4, the generated static electricity can be removed promptly if the power supply line 16 is grounded.
After the thin film transistor panel is cut along the cut line 2 in the manufacturing process of the thin film transistor panel, it is possible for the cut panel to be brought into contact with another substance charged with static electricity. In this case, the protective ring 13, all the scanning signal lines 9 and all the data signal lines 10 can be allowed to bear the same potential by turning on appropriately the protective thin film transistors included in the protective elements 14 and 15. Incidentally, the protective thin film transistors included in the protective elements 14 and 15 do not adversely effect the normal display drive of the liquid crystal display device equipped with the thin film transistor panel.
In the conventional manufacturing method of the thin film transistor panel described above, particularly, in the second photoresist forming step S4 and the anodic oxidation step S5 shown in FIG. 21, the second photoresist films 29a, 29b are formed, subjected to the anodic oxidation treatment and, then, the second photoresist films 29a, 29b are peeled off, giving rise to the problem that the number of manufacturing steps is increased.
It should also be noted that, if the connection pad 18 is formed by arranging the upper layer connection pad 18b consisting of the ITO film on the lower layer connection pad 18a consisting of the Al-based metal film as shown in FIG. 30, the contact characteristics between the Al-based metal film and the ITO film are rendered poor. If the ITO film on the lower layer connection pad 18a consisting of the Al-based metal film is removed in order to overcome the above-noted problem, the exposed Al-based metal film is dissolved in the etchant of the ITO film. Also, if the Al-based film is in contact with the ITO film, the Al-based metal film is oxidized by the etchant of the ITO film, with the result that the ITO film is reduced, giving rise to the problem that both the Al-based metal film and the ITO film are corroded by the so-called xe2x80x9ccell reactionxe2x80x9d.
An object of the present invention is to provide a method of manufacturing a thin film transistor panel, which permits decreasing the number of manufacturing steps and also permits preventing the occurrence of the cell reaction so as to improve the contact characteristics with the connection pad.
According to the present invention, there is provided a method of manufacturing a thin film transistor panel, comprising the steps of forming a scanning signal line including a connection pad and a gate electrode section, the entire region of which includes the surface, being formed of a conductive metal film, on a substrate, forming a gate insulating film on the substrate and the scanning signal line, forming a semiconductor film on the gate insulating film, forming a protective film-forming film on the semiconductor film, patterning the protective film-forming film by a dry etching so as to form a protective film in that region of the semiconductor film which corresponds to the gate electrode section, forming a drain electrode connected to one region of the semiconductor film exposed to the outside from both sides of the protective film and forming a source electrode connected to the other region, forming an upper insulating film to cover the drain electrode, the source electrode and the gate insulating film, and forming a transparent electrode connected to the source electrode on the upper insulating film.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.